1. Field of the Invention
This invention relates to a poly fuse, and more particularly, to the architecture of poly fuses, which have a sheet-like etching stop layer.
2. Description of Related Art
Yield is one of the most important factors regarding the fabrication of semiconductor devices. An entire semiconductor memory device has to be abandoned even if there is only one defective memory cell within the device. It is obvious that more defects occur during the fabrication process of a semiconductor device as the integration of the device increases. In the other words, as the integration of a semiconductor device increases the corresponding yield of the device decreases.
Because of the density of memory cells within a semiconductor memory is increasing, memory fabrication techniques become more difficult and complicated. Since it is impossible to eliminate the presence of particles or crumblings, which decreases the yield, during a fabrication process of a semiconductor device, a so-called redundancy circuit is conventionally used to make up the desired yield of a semiconductor memory. A redundant memory cell array is provided in the so-called redundancy circuit technique besides the regular memory array used to store binary data, wherein the redundant memory array replaces the defective memory cells within the regular memory array. Each of the memory cells within the redundant memory cell array is individually connected to the corresponding wordline and bitline. If a number of the memory cells found to be defective within the regular memory array is somewhere in the order of thousands after the test, the memory cells within the redundant memory cell array replace those memory cells found to be defective to make the memory still an irreproachable one.
The conventional redundancy circuit technique surely can improve the yield of a semiconductor memory, but under a condition that the number of defective memory cells within the regular memory array is less than the number of redundant memory cells within the redundant memory cell array. As long as the number of defective memory cells within the regular memory array is less than the number of redundant memory cells within the redundant memory cell array, the defective memory cells can be replaced by the redundant memory cells to resulting in a perfect memory. However, if the number of defective memory cells within the regular memory array exceeds the number of redundant memory cells within the redundant memory cell array, the semiconductor memory has to be abandoned because there are not enough redundant memory cells to substitute for the defective memory cells. As described above, within a conventional semiconductor memory, it is common to have a redundant memory cell array around the regular memory cell array to replace defective memory cells in case defects occur to enable the memory to remain defect-free. Generally, the regular memory cell array and the redundant memory cell array in a conventional memory are connected through poly fuses, which can be broken by a laser beam or an electrical current. In the case that a defective memory cell is found and needs to be recovered, the corresponding poly fuse is broken by a laser beam or an electrical current; if there are no defective memory cells found, poly fuses remain connected.
FIG. 1 shows a cross-sectional view of the architecture of a conventional poly fuse. As shown in FIG. 1, there are fuses 12 located on a provided substrate 10, wherein the fuses include polysilicon. A dielectric layer 14 is formed through a low pressure chemical vapor deposition (LPCVD) process on the substrate 10 and the fuses 12, wherein the dielectric layer 14 includes silicon dioxide. Then, an etching stop layer 16 is formed on the dielectric layer 14 through a reactive sputtering process, wherein the etching stop layer 16 includes silicon nitride. Then, a passivation layer 18 is formed on the etching stop layer 16 through a chemical vapor deposition (CVD) process, wherein the passivation layer 18 includes silicon dioxide.
FIG. 2 is a top view showing the architecture shown in FIG. 1. The large-area, plate-like etching stop layer 16 is used to protect the fuses 12 from being damaged. In the case that a defective memory cell is found, the corresponding fuse is broken by an electrical current or a laser beam, so that the redundant memory cell can be used to replace the defective memory cell to recover the defect. However, the large-area, plate-like etching stop layer 16 disperses the laser used to break fuses. In result, the large-area, plate-like etching stop layer 16 causes the laser beam to waste energy and a low recovery rate for the defective memory cells.
In fact, the recovery rate for the defective memory cells is only about 50% or even lower with an laser of power at about 2.times.10.sup.-6 -3.times.10.sup.-6 Joules. Increasing the power of laser does raise the recovery rate for the defective memory cells, but it also damages the wafer.
According to the foregoing, the architecture of conventional fuses has drawbacks including:
1. The large-area, plate-like etching stop layer 16 disperses the laser used to break fuses causes the laser beam to waste energy and a low recovery rate for the defective memory cells; and PA1 2. A laser with a higher energy increases the recovery rate for the defective memory cells, but it also causes damages on the wafer.